The use of programmable logic controllers or PLCs to control machine tools such as punch presses, screw machines and automatic welders is well-known. The PLCs contain microprocessors operating under a set of sequential instructions to sense the condition of the machine tool, and to provide outputs for controlling the closing and opening of valves and switches to operate the machine tool.
Previously, some of these PLCs have used a control processor and scan processor arrangement to increase the processing of status and control information. In one such PLC, the control processor assigned certain instructions to the scan processor, and when the scan processor finished, the control processor assigned another routine to the scan processor. For that reason, the scan processor never needed a separate readable program counter because it only performed inline routines and never needed to save the contents of the program counter to do a subroutine.
It would be desirable to operate this PLC with subroutines fetched directly from a user compiled memory so as to expedite the operation of the PLC and to identify the different error conditions occurring in the scan processor so that the control processor can determine if the error was momentary or continuous and act accordingly.